Yongan (Luke) Zhang  

I received my Ph.D. from Georgia Tech in 2025, and my M.S. from Rice University in 2023. My advisor is Prof. Yingyan (Celine) Lin. I received my B.S. from Rice University. My research focuses on AI-enabled hardware design automation and software/hardware co-design for efficient AI.

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A scalable LLM-driven framework for an automated loop of Verilog design generation and assertion-guided functional refinement. SLAVA aims to shift the role of LLMs from passive code generators to active design agents engaged throughout the hardware-development process.

A full-stack and flexible hardware accelerator design framework, integrating a specialized workload and resource partition scheme, a run-time scheduler, and a micro-architecture design targeting Codec Avatars applications and beyond.

An automated framework for data generation and validation, designed to enhance the fine-tuning of Large Language Models (LLMs) in accelerator code generation.

A DNN chip generator that can automatically generate both FPGA-and ASIC-based DNN accelerator implementation (i.e., synthesizable hardware and deployment code) with optimized algorithm-to-hardware mapping.

An automated demo-augmented prompt-generation pipeline utilizing in-context learning to guide LLMs towards creating high-quality AI accelerator design.

Silicon-validated dedicated EGM-to-ECG processor, with continuous lightweight anomaly detection, event-driven coarse/precise conversion, and on-chip adaptation

An automatically search framework for (1) efficient Deep Neural Network (DNN) structures and then (2) corresponding accelerators, to enable Real-Time and high-quality Reconstruction of ECG signals from EGM signals

A GNN and accelerator co-search framework that can automatically search for matched GNN structures and accelerators to maximize both task accuracy and acceleration efficiency.

A novel hardware accelerator for GCN inference that significantly improves data locality and reduces unnecessary computation through a new online graph restructuring algorithm we refer to as islandization.

A Differentiable Accelerator Network Co-Search framework for automatically searching for matched networks and accelerators to maximize both the accuracy and efficiency

Automated Agent Accelerator Co-Search (A3C-S) framework, which automatically co-searches the optimally matched DRL agents and accelerators that maximize both the test scores and hardware efficiency.

An automated framework enabling jointly searching for the Networks, Bitwidths, and Accelerators, by efficiently localizing the optimal design within the huge joint design space for each target dataset and acceleration specification.

Design and source code from Jon Barron's website.